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Espressif Systems /ESP32-S3 /ASSIST_DEBUG /CORE_0_RCD_PDEBUGENABLE

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Interpret as CORE_0_RCD_PDEBUGENABLE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CORE_0_RCD_PDEBUGENABLE)CORE_0_RCD_PDEBUGENABLE

Description

core0 pdebug configuration register

Fields

CORE_0_RCD_PDEBUGENABLE

Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC

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Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data